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principle of localitytemporal base locality locality in time- if an item is referenced then it will tend to be referenced again soonspatial
applications of microprogrammingmicroprogramming application emulationo use of a micro program on 1 machine to execute programs initially
performance of pipelines with stallsa stall is reason of the pipeline performance to degrade the ideal performance
bubbling the pipelinebubbling the pipeline also known as a pipeline break or pipeline stall is a technique for preventing structural data and branch
eliminating hazards of pipeline - computer architecturewe can delegate the work of eliminating data dependencies to the compiler which can fill
hazard in pipeline - computer architecturea hazard in pipeline-removing a hazard frequently need that some instructions in the pipeline to be
branch control hazards in computer architecturebranching hazards also called control hazards take place when the processor is told to branch -for
structural hazards - computer architecturea structural hazard takes place when a part of the processors hardware is required by 2 or more than two
hazard computer architecturein the computer architecture a hazard is a possible problem that can occurs in a pipelined processor it concern to the
hazards of pipeline - computer architecturehazards when a programmer or compiler writes assembly program code they make the supposition that each
disadvantages of pipelinepipeline architecture has 2 major disadvantages first is its complexity and second is the inability to constantly run
types of pipelinesinstructional pipeline it is used where different stages of an instruction fetch and execution take place in a
pipelining - computer architecturethe pipeline definedaccording to john hayesa pipeline processor consists of a sequence of processing circuits
comparison between risc and cisc - computer architecturecisc emphasis on hardware includes multi-clockcomplex
risc approach - computer architecturethe risc processors only use easy instructions that can be executed within one clock cycle therefore the mult
cisc approach - cisc architecturethe main goal of cisc architecture is to finish a task in as few lines of assembly as possible as this is gain by
need of cisc cpu - computer architecturewhy is intel spending money and time to manufacture the pentium ii and the pentium iiithe answer of this
risc architecture - computer architecturewhat is reduced regarding it the answer of this question is that to make all instructions the equal
reduced instruction set computer riscas we discussed before most of the modern cpus are of the gpr general purpose register type a few instances of
advantages of instruction set architecturestackadvantages it is simple model of expression evaluation reverse polish contain short
accessing the operandsoperands are usually place in one of two places-registers 32 int 32 fp-memory 232locationsregisters are-simple to specify-shut
displacement and stack addressing mode - computer architecturedisplacement addressingin displacement addressing mode there are three types of
register addressing mode - computer architectureregister addressingregister addressing mode is same to direct addressing only difference in between
indirect addressing mode - assembly languagethe indirect addressing mode and the address field of the instruction refers to the address of a word in
direct addressing and immediate addressing mode - computer architecture immediate addressingit is the simplest form of addressing here the