Start Discovering Solved Questions and Your Course Assignments
TextBooks Included
Active Tutors
Asked Questions
Answered Questions
what is asynchronous resetasynchronous resetthe biggest problem along with asynchronous resets is the reset release which termed as reset removal by
what is synchronous resetsynchronous resetsynchronous reset logic will synthesize to smaller flip-flops mainly when the reset is gated along with the
you have two counters counting up to 16 built through negedge dff first circuit is synchronous and second is ripple as cascading which circuit has a
the circle can rotate clockwise and back by using minimum hardware build a circuit to indicate the direction of rotatingtwo sensors are required to
is it possible to decrease clock skew to zero describe your answer even if there are clock layout strategies h-tree which can into theory reduce
what is difference between ram and fifofifo certainly does not have address lines it is stands for first in and first out it is an algorithm based
what is difference between hold time and setup the interviewer was looking for one exact reason and itrsquos really a good answer as wellthe hint is
an assembly line consists of 3 fail safe sensors and one emergency shutdown switch the line must keep moving unless any of the given conditions
what is race-around problem how can you rectify thisthe clock pulse which remains into the 1 state whereas both j and k are equal to 1 will reason
n number of xnor gates is linked in series that is the n inputs a0 a1 a2 are specified in the subsequently way a0 and a1 to first xnor gate and a2
design a circuit which computes the square of a numberthis should not make use of any multiplier circuits this should use multiplexers and some other
what are set up time and hold time constraints what do they mean which one is crucial for establishing maximum clock frequency of a circuitset up
given the subsequent fifo and rules how deep does the fifo require to be to stop underflow or overflowrules a frequencyclka frequencyclkb 4 b
what will occur when contents of register are shifter left rightthis is well known that into left shift all bits will be shifted left and lsb will be
explain why most interrupts are active lowthis answers why most signals are active low when you see the transistor level of a module active low
describe some of applications of bufferapplications of buffera they are utilized to introduce tiny delaysb they are utilized to eliminate cross talk
what is importance of ras and cas in sdramsdram acquires its address command into two address words this uses a multiplex scheme to save input pins
how to attain 180 degree precise phase shiftnever tell using invertera dcm an inbuilt resource into most of fpga can be arranged to get 180 degree
what are the differences between one hot and binary encodingcommon classifications used to explain the state encoding of an fsm is binary or highly
what are the advantages and disadvantages of mealy and moore state machineadvantage and disadvantage of mealy and moore state machinein mealy as the
what are difference between mealy and moore state machinedifference between mealy and moore state machine1 mealy and moore models are the fundamental
differentiate the latch and flip-flopthe major difference between latch and ff is which latches is level sensitive whereas ff is edge sensitive they
illustrate what are the multimedia applicationsmultimedia comprise the use of a computer to present- text- video- graphics- sound- animationin an
real time transaction processing in real time transaction processing files are generally updated in real time for example when booking flights on an
how sensors uses in real time process controlsensors send data through an analogue to digital converter - adc to a microprocessor or computer that