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what are latches and flipflopsthere are two types of circuits as followsa combinationalb sequentialflipflops and latches both come into the category
what is fifo fifo is used as buffering element or queuing element into the system that is by common sense is needed only while you slow at reading
what are differences between synchronous asynchronous and i synchronous communicationsending data encoded in your signal needs that the sender and
how are problems of clock skew minimizedclock skew when done right can also benefit a circuit this can be intentionally introduced to reduce the
what are problems of clock skewthis is typically because of two causes the primary is a material flaw that causes a signal to travel faster or slower
what is skewclock skewin circuit design clock skew is a phenomenon within synchronous circuits wherein the clock signal sent through the clock
what is difference between write back and write through cachea caching method wherein modifications to data into the cache arent copied to the cache
what are the difference between heap and stackthe stack is more or less responsible for maintaining track of whats executing into our code or whats
what is slackslack is the amount of time you have which is measured through while an event lsquoreally happens and while it lsquoshould
what are disadvantages of the asynchronous reset and synchronous resetdisadvantages of asynchronous resetmake sure that the release of the reset can
what is asynchronous resetasynchronous resetthe biggest problem along with asynchronous resets is the reset release which termed as reset removal by
what is synchronous resetsynchronous resetsynchronous reset logic will synthesize to smaller flip-flops mainly when the reset is gated along with the
you have two counters counting up to 16 built through negedge dff first circuit is synchronous and second is ripple as cascading which circuit has a
the circle can rotate clockwise and back by using minimum hardware build a circuit to indicate the direction of rotatingtwo sensors are required to
is it possible to decrease clock skew to zero describe your answer even if there are clock layout strategies h-tree which can into theory reduce
what is difference between ram and fifofifo certainly does not have address lines it is stands for first in and first out it is an algorithm based
what is difference between hold time and setup the interviewer was looking for one exact reason and itrsquos really a good answer as wellthe hint is
an assembly line consists of 3 fail safe sensors and one emergency shutdown switch the line must keep moving unless any of the given conditions
what is race-around problem how can you rectify thisthe clock pulse which remains into the 1 state whereas both j and k are equal to 1 will reason
n number of xnor gates is linked in series that is the n inputs a0 a1 a2 are specified in the subsequently way a0 and a1 to first xnor gate and a2
design a circuit which computes the square of a numberthis should not make use of any multiplier circuits this should use multiplexers and some other
what are set up time and hold time constraints what do they mean which one is crucial for establishing maximum clock frequency of a circuitset up
given the subsequent fifo and rules how deep does the fifo require to be to stop underflow or overflowrules a frequencyclka frequencyclkb 4 b
what will occur when contents of register are shifter left rightthis is well known that into left shift all bits will be shifted left and lsb will be
explain why most interrupts are active lowthis answers why most signals are active low when you see the transistor level of a module active low