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in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk if yes why yes in a pure combinational circuit is it
what is the difference between the following two lines of verilog code 5 a b a 5 b5 a b wait five time units before doing the action for a b
differences between inter statement and intra statement delay define register variablesreg a b cintra assignment delaysinitialbegina 0 c 0b 5 a c
how can i model a bi-directional net with assignments influencing both source and destination assign statement constitutes a continuous assignment
determine the uses of memory blocks not as common a technique though something to consider as verilog has a very convenient syntax for declaring and
state the use parameters and parameter definition modules parameters arent preprocessor definitions and they have scope for example parameters are
state the term- use a define function this is almost exactly the same approach as define and -d compiler arg that c programs use in your
how can i pass parameters to my simulationa test bench and simulation would likely need many different
can i use a verilog function to define the width of a multi-bit port wire or reg typewidth elements of ports wire or reg
how is the connectivity established in verilog when connecting wires of different widthswhen connecting wires or ports of different widths
what happens to logic after synthesis which is driving an unconnected output port that is left open that is noconnect during its module
the disadvantages of specifying parameter assignments using defparam are- parameter is essentially specified by the scope
state the advantages of specifying parameter assignments using defparam are- this method always has precedence over specifying parameters at the
the disadvantage of specifying parameter during instantiation are- this has a lower precedence when compared to assigning using
the advantages of specifying parameters during instantiation method are- all values to all the parameters do not need to be specified only those
using module-instance parameter parameter values can be overridden while a module is instantiated new parameter values are passed at the time of
using defparamparameter values can be changed in any module instance in the design with keyword defparam hierarchical name of the module instance can
for what is defparam usedthough during compilation of verilog modules parameter values can be altered
determine the example of timescaletimescale 10ns 1ps indicates delays are in 10 nanosecond units with 3 decimal points of precision1 ps is 11000ns
state the tips of timescale directiveinclude a timescale directive at the top of each module even if there are no delays i n the module since some
what are the rules of timescale directiverules- timescale directive like all compiler directives affects all modules compiled after directive
what is the significance timescale directive defines time units and simulation precision smallest incrementsyntaxtimescale timeunit
reg data type as sequential elementmodule regseqexample clk reset d qinput clk reset doutput qreg qwire clk reset dalways posedge clk or posedge
reg data type as combinational elementmodule regcomboexample a b yinput a boutput yreg ywire a balways a or bbeginy a amp bendendmodulethis gives
what is the difference between wire and regwirewire is used for designing combinational logic as we all know that this type of logic cannot store a