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what are the various design constraints used while performing synthesis for a design1 make the clocks frequency duty-cycle2 explain the
what are the advantages and drawbacks of mealy and moore machineadvantages and drawbacksinto mealy as the output variable is a function both state
what are advantages and drawbacks of flip-flopusually area of a flip-flop for features in more than a latchpower consumption is normally higher
what does formal verification mean formal verification uses mathematical techniques by proving the design by assertions or properties correctness of
what are advantages and drawbacks of latchesadvantages and drawbacks of latchesarea of a latch is classically less than a flip flopit consumes less
we have multiple instances in rtl register transfer language do you do anything special during synthesis stagewhereas writing rtlregister transfer
what do you call an event and when do you call an assertionassertion based verification tools checks whether a statement holds a explained
what is the difference between latches and flip-flops based designslatches are level sensitive whether flip-flops are edge sensitive so latch based
describe the types of flip-flops and latchesflip-flops are of two types as illustrated belowa positive edge triggeredb negative edge
what are the measures or precautions to be taken in the design when the chip has both analog and digital portionsas todays ic has analog components
how to increase simulation speed first figure out what is eating away your cpu cycles is it1 compile time - use a make file to compile
how do you find out the flaw which of the address getting written wrongly fill the full memory once with either random data or sequential data then
how the temperature effecting the delays in a chip the delays are directly proportional to the temperatureas the temperature enhances the delays are
what are difference between latches and flipflopsdifference latches are level-sensitive while flipflops is edge sensitive it means to say edge
difference among the static rams and dynamic ramsstatic ramit is costly as each bit of memory will take around 6 cmos transistorsmore speedy as
what are latches and flipflopsthere are two types of circuits as followsa combinationalb sequentialflipflops and latches both come into the category
what is fifo fifo is used as buffering element or queuing element into the system that is by common sense is needed only while you slow at reading
what are differences between synchronous asynchronous and i synchronous communicationsending data encoded in your signal needs that the sender and
how are problems of clock skew minimizedclock skew when done right can also benefit a circuit this can be intentionally introduced to reduce the
what are problems of clock skewthis is typically because of two causes the primary is a material flaw that causes a signal to travel faster or slower
what is skewclock skewin circuit design clock skew is a phenomenon within synchronous circuits wherein the clock signal sent through the clock
what is difference between write back and write through cachea caching method wherein modifications to data into the cache arent copied to the cache
what are the difference between heap and stackthe stack is more or less responsible for maintaining track of whats executing into our code or whats
what is slackslack is the amount of time you have which is measured through while an event lsquoreally happens and while it lsquoshould
what are disadvantages of the asynchronous reset and synchronous resetdisadvantages of asynchronous resetmake sure that the release of the reset can