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define a gate fix asic-based design in shortgate fix asic-based designa gate fix implies that a select number of gates and their interconnections may
explain about the term rtl fixrtl fixan rtl fix implies you change the verilogvhdl code and you resynthesize this generally means a new plance and
how to fix an asic-based design from easiest to most extremethere are different ways to fix an asic-based design as given belowinitially assume some
what is basic analog designanalog design is rather challenging than digital design as analog circuits are sensitive to noise operating voltages
what is the fundamental digital designdigital design is distinct through analog design in analog circuits we deal along with physical signals that
what is clock gating clock gating is one of the power-saving methods used on several synchronous circuits with the pentium four processors to save
explain the term- scan insertion scan insertion is completed by a tool and results in all or most of your designs flip-flops to be changed by special
what is scanscan insertion and atpg helps test asics eg chips during manufacture if you know what jtag boundary scan is then scan is the similar idea
what are differences between one hot and binary encodingcommon classifications used to explain the state encoding of an fsm is binary or highly
what is boundary scan boundary scan is a board level design method that provides test access to the input and output pads of ics on pcbs boundary
what are the various design constraints used while performing synthesis for a design1 make the clocks frequency duty-cycle2 explain the
what are the advantages and drawbacks of mealy and moore machineadvantages and drawbacksinto mealy as the output variable is a function both state
what are advantages and drawbacks of flip-flopusually area of a flip-flop for features in more than a latchpower consumption is normally higher
what does formal verification mean formal verification uses mathematical techniques by proving the design by assertions or properties correctness of
what are advantages and drawbacks of latchesadvantages and drawbacks of latchesarea of a latch is classically less than a flip flopit consumes less
we have multiple instances in rtl register transfer language do you do anything special during synthesis stagewhereas writing rtlregister transfer
what do you call an event and when do you call an assertionassertion based verification tools checks whether a statement holds a explained
what is the difference between latches and flip-flops based designslatches are level sensitive whether flip-flops are edge sensitive so latch based
describe the types of flip-flops and latchesflip-flops are of two types as illustrated belowa positive edge triggeredb negative edge
what are the measures or precautions to be taken in the design when the chip has both analog and digital portionsas todays ic has analog components
how to increase simulation speed first figure out what is eating away your cpu cycles is it1 compile time - use a make file to compile
how do you find out the flaw which of the address getting written wrongly fill the full memory once with either random data or sequential data then
how the temperature effecting the delays in a chip the delays are directly proportional to the temperatureas the temperature enhances the delays are
what are difference between latches and flipflopsdifference latches are level-sensitive while flipflops is edge sensitive it means to say edge
difference among the static rams and dynamic ramsstatic ramit is costly as each bit of memory will take around 6 cmos transistorsmore speedy as