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using defparamparameter values can be changed in any module instance in the design with keyword defparam hierarchical name of the module instance can
for what is defparam usedthough during compilation of verilog modules parameter values can be altered
determine the example of timescaletimescale 10ns 1ps indicates delays are in 10 nanosecond units with 3 decimal points of precision1 ps is 11000ns
state the tips of timescale directiveinclude a timescale directive at the top of each module even if there are no delays i n the module since some
what are the rules of timescale directiverules- timescale directive like all compiler directives affects all modules compiled after directive
what is the significance timescale directive defines time units and simulation precision smallest incrementsyntaxtimescale timeunit
reg data type as sequential elementmodule regseqexample clk reset d qinput clk reset doutput qreg qwire clk reset dalways posedge clk or posedge
reg data type as combinational elementmodule regcomboexample a b yinput a boutput yreg ywire a balways a or bbeginy a amp bendendmodulethis gives
what is the difference between wire and regwirewire is used for designing combinational logic as we all know that this type of logic cannot store a
syntax of display and strobe- display formatstring par1 par2 - strobe formatstring par1 par2 - monitor formatstring par1 par2 -
state the term in detail strobestrobe this task is very similar to display task except for a slight difference if many other statements are
what are the difference between display and strobedifference between display and strobe is that strobe displays parameters at the very end of current
state the term- display and writedisplay and write two are the same except which display always prints a newline character at the end of its
differentiate between display and strobethese commands have similar syntax and display text on screen during simulation display and strobe display
write decoder functionality in only one statement in verilog ltcodegtmodule decoder outputsdout inputsdininput 30 dinoutput 150 doutassign dout
explain the term- signals- signals are used for communication between components- signals can be seen as real physical signals- some
explain the term- variables- variables are used for local storage of data- variables are usually not available to multiple processes and
what are the various functional verification methodologiesans tlm transaction level modellinglintingrtl simulation environment involving
state the optimal route of nodeconsider the node i which has path length k1 with the directly preceding node on the path being j the distance to node
what is reentrant tasks and functionstasks and functions without optional keyword automatic are static with all declared items being statically
why disable statements are not allowed in functionsif disble statement is used in functionit invalids function and
why a function canot have delayshowever in open vera delays are allowed in function a function returns a value and hence can be used as a part of any
why a task cannot return a valueif tasks can return values then lets take a look at the below exampleaf1bf2cand f1 and f2 had delays of say 5 and 10
why a function should have at least one inputthere is no strong reason for this in verilog i think this restriction isnt removed fin systemverilog
why a function cannot call a taskas functions doesnt consume timeit can do any operation which doesnt consume time mostly tasks are written that