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Explore the trade-off between input common-mode range and differential gain in the design of the bipolar BJT.
What is the largest possible input common-mode voltage for which operation is as required? Assume a ? 1.
With no emitter resistances Re, use the large-signal model to find iC1 and iC2 when vid = 20 mV.
What is the maximum allowable value of the input common-mode voltage, VCM? Recall that to maintain an npn BJT in saturation.
Sketch the circuit and give its differential half-circuit. If VA =20 Vfor all transistors, find the differential voltage gain achieved.
Operate all transistors at VOV = 0.15 V and assume that for the process technology in which the circuit is fabricated, Vtn = 0.4 V and µnCox = 400 µA/V2.
Use Eq. to show that if the term involving v2 id is to be kept to a maximum value of k then the maximum possible fractional change .
Design a MOS differential amplifier to operate from ±1-V power supplies and dissipate no more than 1 mW in the equilibrium state.
At what overdrive voltage will each of Q1: and Q2: be operating when vid = 0?
Specify the W/L ratios and the bias current. The technology available provides Vt =0.5 V and µnCox =400 µA/V2.
Design a MOS differential amplifier to operate from ±1-V supplies and dissipate no more than 1 Mw in its equilibrium state.
If each of the two transistors is operating at an overdrive voltage VOV = 0.2 V, what must the value of I be?
A MOS differential amplifier is designed to have a differential gain Ad equal to the voltage gain obtained from a common-source amplifier.
A differential amplifier is designed to have a differential voltage gain equal to the voltage gain of a common-source amplifier.
Figure shows Amos differential amplifer with the drain resistors RD implemented using diode-connected PMOS transistors,Q3: and Q4.
Find the differential half-circuit for the differential amplifier shown in Fig. and use it to derive an expression for the differential gain Ad = vod /vid .
Assume that Q1: and Q2: are matched and operate in saturation at an overdrive voltage VOV that corresponds to a drain bias current of I/2.
The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1: and Q2: is not shown.
The differential gain Ad in terms of RD, I, and VOV Now design the amplifier to obtain a differential gain of 500 V/V.
Find IO1 and IO2 in terms of IREF. Assume all transistors to be matched with current gain ß.
For the Wilson current mirror of Fig.,show that the incremental input resistance seen by IREF is approximately 2VT /IREF.
Assume that all three transistors are identical and neglect the Early effect. Also, assume a signal ground at the output.
The current source is required to operate with the voltage at its output terminal as low as -2.5 V.
Utilizing a reference current of 200 µA, design a Widlar current source to provide an output current of 20 µA. Assume ß to be high.
Find the value of R that yields a current I = 200 µA. For the BJT, VEB = 0.7 V at IE = 1 mA.