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Find the dc voltage at the output. Assume /VBE /= 0.7V, ß = 100, and neglect the Early effect.
Now, using ß=100, find the voltage gai vo/(v+ -v-), and in the process, erify the polarity of the input terminals.
Show that if all transistors are operated at an overdrive voltage VOV and have Equal Early voltages /VA .
Find the currents labeled i1 to i13 in terms of (gmvid ). Determine their values in the sequence of their numbering and assume gmro.
This problem investigates the effect of transistor mismatches on the input offset voltage of the current-mirror-loaded MOS differential amplifier.
What will the voltage gain be if the input resistance of the subsequent stage is equal to Rid of this stage?
For the current-mirror-loaded bipolar differential pair, replacing the simple current-mirror load by the base-current-compensated mirror.
What should the value of VBIAS be in order to allow for a negative output signal swing of 1.5 V?
With vI =0 V dc, find the input bias current IB assuming all transistors have equal value of ß. Compare with the case without the Q7:Q8:connection.
If I is delivered by a simple NMOS current source operated at the same VOV and having the same channel length as the other four transistors.
Recalling that for the simple mirror RSS = ro/ QS and for the Wilson mirror RSS ?gm7ro7ro5, and assuming that all transistors have the same /VA / and k1W/L.
If the common-mode output resistances of the amplifier, Ro1 and Ro2, are very large, find Acm and CMRR.
What is the expected magnitude of the deviation from unity of the current gain of the load mirror?
What is the value of the input common-mode resistance when the bias source has the lowest acceptable output resistance?
If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch.
If the output resistance of the current source is 500 kO and the resistance in each collector (RC) is 12 kO, find the common-mode gain .
An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 kO ± 1%. For the pair, K? nW/L =4 mA/V2.
If the output is taken differentially and there is a 1% mismatch between the drain resistances, find /Ad / , / Acm / , and CMRR.
Find expressions for Ad and VOS in terms of kn, RD, ?RD/RD, and I. Use these expressions to relate VOS and Ad .
An NMO Samplifier, whose designed operating point is at VOV =0.3 V, is suspected to have a variability of Vt of ±5 mV, and of W/L.
Find the three components of input offset voltage under the conditions that ? RD/RD = 4%, ? (W/L)/(W/L) = 4%, and ?Vt = 5 mV.
Two possible differential amplifier designs are considered, one using BJTs and the other MOSFETs.
A differential amplifier uses two transistors having VA values of 100 V and 200 V.
A differential amplifier for which the total emitter bias current is 400 µA uses transistors for which ß is specified to lie between 80 and 200.
In a particular BJT differential amplifier, a production error results in one of the transistors having an emitter-base junction area twice that of the other.