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How does a coprocessor recognize a 68020 access? The 68040's approach to bus arbitration differs from that of the 68000 to the 68030. In what way?
Why is it much harder to design a data cache than an instruction cache? To what extent do the 68020's instruction cache and the 68030's instruction.
what must the value of h be to achieve this? assume that the main store access time is 150 ns and that the cache access time is 30?
Why is the performance of the direct-mapped cache much worse than that of a fully associative cache under certain circumstances?
How would you program the PMMU's TC register to implement a two-level page system with a page size of 8 Kbytes and a 30-bit logical address?
Why are both these descriptors available in long and short forms, and what effect does this have on the address translation process?
Why can the 68010, the 68020, etc., be used to design virtual memory systems? How does the PMMU avoid the need for a vast number of page descriptors?
Describe how the 68451 MMU translates logical addresses into physical addresses. List the advantages and disadvantages of 68451's approach to memory management.
What are the main objectives of a memory management system? What is the difference between logical and physical address space?
What are the fundamental differences between EPROM, flash EEPROM, and E 2 PROM?
What are the criteria by which address decoders are judged? What does primary address range mean when it is applied to a system using partial address decoding?
A 68000 system is to have up to eight 512 K-word pages of read/write memory, up to eight 16 K-word pages of EPROM. Design an arrangement that will do this.
What is meant by the terms partial address decoding and full address decoding? What, if any, are the dangers inherent with this system?
Can you think of any way of overcoming the restriction that a block of memory should be mapped onto a boundary equal to its own size?
Design an address decoder for the following 68000 system: 256 Kbytes of ROM (using 128K x 8-bit chips) and 4 Mbytes of RAM1 (using 512K x 4-bit chips).
Assume that we are using a 68000-based system. What 68000 address lines are required to address each of the memory blocks in Ql?
If you had to design a 32-bit address and data interface to a modern microprocessor, how would you go about it? What functions would you include?
What is a read-modify-write cycle, and what is the difference in the way in which the 68000 and the 68020 implement it?
Design a universal programmable interface that can connect almost any peripheral to a 68000 system-even if the peripheral has unusual timing restrictions.
Design a circuit that would assert both BERR* and HALT* for a rerun bus cycle, whenever a signal, MEMORY_ERROR*, is asserted.
What is a double bus fault and why is it described as fatal? If you were a systems designer, what would you do to attempt to make your system hacker-proof?
Why does the location of the 68000s reset vectors cause the system designer so many problems? What is the exception with the highest priority?
After an exception, the program counter is saved on the supervisor stack. What does this value of the PC point at?
What are the differences between TRAPS, illegal instruction exceptions, and line A and line F exceptions?
You decide to use the 68000's line 1010 emulator trap. Show how you would do this. Remember that the instruction will have the form.