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Can you think of any way of overcoming the restriction that a block of memory should be mapped onto a boundary equal to its own size?
Design an address decoder for the following 68000 system: 256 Kbytes of ROM (using 128K x 8-bit chips) and 4 Mbytes of RAM1 (using 512K x 4-bit chips).
Assume that we are using a 68000-based system. What 68000 address lines are required to address each of the memory blocks in Ql?
If you had to design a 32-bit address and data interface to a modern microprocessor, how would you go about it? What functions would you include?
What is a read-modify-write cycle, and what is the difference in the way in which the 68000 and the 68020 implement it?
Design a universal programmable interface that can connect almost any peripheral to a 68000 system-even if the peripheral has unusual timing restrictions.
Design a circuit that would assert both BERR* and HALT* for a rerun bus cycle, whenever a signal, MEMORY_ERROR*, is asserted.
What is a double bus fault and why is it described as fatal? If you were a systems designer, what would you do to attempt to make your system hacker-proof?
Why does the location of the 68000s reset vectors cause the system designer so many problems? What is the exception with the highest priority?
After an exception, the program counter is saved on the supervisor stack. What does this value of the PC point at?
What are the differences between TRAPS, illegal instruction exceptions, and line A and line F exceptions?
You decide to use the 68000's line 1010 emulator trap. Show how you would do this. Remember that the instruction will have the form.
Write a trace exception handling routine that displays the contents of registers whenever an instruction is executed that falls between two addresses.
What does context switching mean, and how can it be implemented (making best use of the 68000's features)?
Each time the button is depressed, IRQ7* is pulled low. Why is it necessary to employ a debounced switch?
Why can you locate some of the additional vectors in the 68000's exception vector table at locations marked unimplemented, reserved?
Design a circuit to generate an interrupt on IRQ1* every T seconds, provided that interrupts IRQ2*-IRQ7* have not been asserted during the previous T seconds.
A print spooler prints one or more files as background jobs while processor is busy executing a job. `Design a basic print spooler that will print a file.
Design the necessary logic interface to make this peripheral look like a 68000-series component.
All ItO had to be polled. Why do you think that this decision has been taken? Hint: Railway control is a high-security application of computers.
Design a hardware filter that would prevent any peripheral supplying a number in the range 0-63 during an JACK cycle.
What is a spurious interrupt and how is it generated? What is the difference between an uninitialized interrupt and a spurious interrupt exception?
Why is RAS*-only refreshing now less popular than CAS*-before-RAS* refreshing? Why does the CAS*-only refresh make it easy to design a refreshing system?
Why must DRAMs be refreshed, and how may a refresh operation be carried out? What effect does it have on the design of DRAM systems?
Why is the value of tRcD (RAS* low to CAS* low) a pseudo maximum value? What factors determine the minimum and maximum values of tRcD?