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question a computer system has a 64 kb main memory and a 4 kb data area only cache there are 8 bytescache line
question show the schematic diagrams of the cache memory in problem assuming that the data and tag areas of the cache
question in problems ii if the cache access time is 100 ns what hit ratio would be required to achieve an average
question a computer system has 128 kb of secondary storage and an 8 kb main memory the page size is 512 bytes design a
question determine the minimum and maximum page-table sizes and the corresponding number of accesses needed to search
question a memory system has the following characteristics access times cache 100 ns main memory 1000 ns tlb 40 ns
question 1 a processor has a direct addressing range of 64 kb show two schematics to extend the address range to 512
question assume that a system has both main-memory and disk caches discuss how write-through and write-back mechanisms
question an example of macroinstruction is a translate instruction the instruction replaces an operand with a
question the instruction set of a machine has the following number and types of instructions ten 3-address instructions
question discuss the relative merits and effects on the instruction cycle implementation of the following
question in a four-address machine the fourth address in the instruction corresponds to the address of the next
question a 32-bit machine needs 250 instructions each 32 bits long all instructions are two-address instructions show
question there are three classes of instructions in an instruction set two-address one address and zero-address all
question what is the storage capacity and maximum data transfer rate ofa a magnetic tape 800 bits per inch 2400 feet
question redesign the memory cell of figure to make it suitable for coincident decoding ie two enable
question arrange the 16 chips needed in the design of problem b as a 4 x 4 array and design the decoding
question a processor has a memory addressing range of 64k with 8 bits per word the lower and upper 4k of the memory
question an 8k memory is divided into 32 equal-size blocks or pages of 256 words each the address bits are then grouped
question four of the 32 pages of the memory of problem must be accessible at any time four auxiliary 5-bit registers
question assume that a dynamic ram controller is available for an 8k ram with multiplexed addresses draw the schematic
question if the processor of problem performs programmed io and each byte of io requires two instructions what
question a processor executes 1000k instructions per second the bus system allows a bandwidth of 5 mb per second assume
question assume that the processor status register of an 8-bit machine contains the following flags carry zero overflow
question determine the micro operations for the add instruction for the machine of problem assuming the memory isa big