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let s f 1 2 3 4 14 15g and let arb mean a b mod n where n is a positive integera prove r is an equivalent relation
consider the following sets w fa b cg y fa bg and z fcga which of these sets are subsets of others or of themselvesb
1 prove that the complement of the ex-or function is equal to its dual2 derive the truth tables for the following
design a multioutput circuit whose input is bcd data and whose outputsw detects numbers that are divisible by 3 andx
a combinational circuit is to be designed to control a seven-segment display of decimal digits the inputs to the
a certain democratic country is ruled by a family of four members a b c and d a has 35 votes b has 40 votes c has 15
1 a 6-to-64 decoder is to be implemented using 3-to-8 decoders only show the block diagram of the 6-to-64 decoder2
1 it is required to design lighting for a room such that the lights may be switched on or off from any one of three
design a combinational circuit to generate the parity bit for digits coded in bcd code the circuit should also have an
a circuit to compare two 4-bit numbers a3-0 and b3-0 is to be designed the status of the comparison is available on the
1 assume a d flip-flop with separate set s and reset r inputs how can this flip-flop be configured such that its output
a d flip-flop is connected as shown determine the output of the flip-flop for ten clock pulses assuming it has
a combinational circuit that generates the square of all the combinations of a 3-bit binary number is to be implemented
a circuit is to be designed to derive the greatest common divisor gcd of two numbers each of which is less than or
1 write the vhdl description for the 5421 code to bcd encoder using a conditional signal assignment statement2 a
using the subtractor designed in exercise 5 as a component write the vhdl code for a 4-bit subtractor employing a
1 write the vhdl code for an 8-bit twos complement addersubtractor circuit which functions as an adder when a select
implement a circuit that will compare two 3-bit binary numbers x x2x1x0 and y y2y1y0 and generate separate outputs
a computing system consists of four processors p1 p2 p3 and p4 and four blocks of memories m1 m2 m3 and m4 processor p1
a combinational circuit is to be designed to generate a parity bit for input digits in bcd code the circuit also has an
1 write the vhdl code to specify a circuit that generates the square of a 3-bit number2 write the vhdl code for a full
minimize the following incompletely specified sequential circuits if possible implement the circuits using d flip-flops
a sequential circuit is to be used to identify possible noncodewords produced by a 3-out-of-6 code generator circuit
a sequential circuit is to be designed to monitor the status of a chemical experiment every 10 s the circuit receives
1 design a counter that can count either in mod-8 pure binary or in mod-8 gray code depending on a control signal being