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1 what are the major manifestations of low-frequency oscillation why is the oscillating frequency among local
1 why is the qr method not suitable for the eigenvalue analysis of large-scale electrical power systems2 what is the
1 what aspects should be considered in choosing appropriate integration methods when numerical integration is used to
1 what suppositions are made within the transient stability analysis model of electrical power systems and what is the
1 what is meant by the transient stability of electrical power systems what methods can be adopted to analyze it how
there are three kinds of coordinates used to describe the electrical quantities of a generator these are the electrical
1 determine if the following hamming codes have damaged data in it provide the corrected data fori even parity scheme
1 truncate the 6-bit fractional fixed-point numbers between 1 an d -1 to forma 2-bitb 3-bitc 4-bit andd 5-bit fractions
a 75 mm long line pq is inclined at an angle of 300 to the hp the end p is 20 mm above the hp and on the vp the end q
the complementary metal-oxide semiconductor cmos technology allows for the availability of a transmission gate tg as
1 the truth table of a 3-input digital device shown in figure 3p2a is given in the table of figure 3p2b obtain the
a single-phase induction motor takes an input power of 280 w at a power factor of 06 lagging from a 110-v supply when
a turbine generator has the following sequence reactancescompare the fault currents for a three-phase fault and a
1 consider the system shown in the single-line diagram of figure 754 all reactances are shown in per unit to the same
an inhibited toggle flip-flop has inputs i0 i1 t and reset and outputs q and qn reset is active high and overrides the
a 4-bit magnitude comparator chip eg 74ls85 compares two 4-bit numbers a and b and produces outputs to indicate whether
a synchronous 4-bit updown decade counter with output q works as follows all state changes occur on the rising edge of
1 implement a 3-to-8 decoder using a lut give the lut truth table and write the vhdl code the inputs should be a b and
write vhdl code to implement the following state table use two processes state changes should occur on the falling edge
in the following code state and nextstate are integers with a range of 0 to 2a explain why a latch would be created
examine the following vhdl code and complete the following exercisesa draw a block diagram of the circuit implemented
a write a behavioral vhdl description of the state machine you designed in problem 113 assume that state changes occur
1 what device does the following vhdl code represent2 a write a vhdl module for a lut with four inputs and three
1 write a vhdl model for a 74hc192 synchronous 4-bit updown counter ignore all timing data your code should contain a
what is the size of the smallest rom that is needed to implement the followinga an 8-bit full adder assume carry-in and