Problem
a) Write VHDL code to generate CLK signal with the specified period using 50 MHz clock signal available on your development board. Use the specified LED to visualize CLK signal.
b) Modify your VHDL code and add another process to create an 8-bit counter driven by CLK signal generated in question 1. Use the switch SW0 to start and stop the counter. Visualize counter value in decimal form with seven-segment indicators HEX2...HEX0.