Problem
• Develop an RTL VHDL description of the Shift/subtract sequential restoring divider for unsigned integers. The circuit generates a correct result (quotient q and remainder r) only for the case of the following relation between the dividend z and the divisor d: z7..4 < d.
• Write Testbench Code covering all possible values of inputs a and x, and reporting any discrepancies between the actual and expected outputs.