Complete the following tasks:
Problem 1: Examine the accompanying data sheet for SN74F163A SYNCHRONOUS 4-BIT BINARY COUNTER component.
Problem 2: Write an RTL VHDL entity and architecture implementing the functionality of this component.
Details:
a. It should have the same logical input/output ports as described in the data sheet
b. You do not have to care about the electrical or physical characteristics
c. You do not need to care about the exact timing characteristics as delays are not synthesizable but depend on the manufacturing technology
d. Use a generic value for the CLK signal (default of 50 MHz). You can add other relevant generic values if you wish e. Do not implement it at gate level as on page 3 of the data sheet, but on register-transfer level.
Problem 3: Using hierarchical design principles, write a VHDL entity and architecture that can count from 0 to 60 (then back to 0, like seconds of clock) using the counters you implemented in part 2. The component should also support the loading and clearing properties of the counter, and all counters should use the same clock signal.
Problem 4: Write a test bench for the hierarchical module. You can decide yourself on the testbench characteristics but remember what has been taught about good testbenches on the course. You can and probably should also write a testbench for the 4-bit counter entity to help debugging.
Problem 5: Simulate your design in Modelsim. Take screen captures of wave forms that show the functionality of your design bug-free.
Tasks 2 and 3 will be graded based on how well the desired functionality is implemented, as described in the data sheet. Task 4 will be graded based on the quality of the testbench. Grading of tasks 2-4 also take into account whether good coding practices have been followed.