Write an ABEL, VHDL, or Verilogprogram for a sticky-counter state machine with eight states, S0 -S7,that are coded into three bits in binary counting order. Besides CLOCK, the machine should have two inputs, RESET and ENABLE, and one output, DONE. The machine should go to state S0 whenever RESET is asserted. When RESET is negated, it should move to next-number state only if ENABLE is asserted. However, once it reaches state S7, it should, it should stay there unless RESET is again asserted. The DONE output should be 1 if and only if the machine is in state S7 and ENABLE is asserted.
A program written in hardware description language (Active HDL 6.3)
The schematic diagram generated through the use of Active HDL 6.3 hardware description language based program.