1.Work Problem 17.E, but change the register to 6 bits, remove the input En, and add an input L. At the rising edge of the clock, if R = 1and L = o, the register shifts right. If R = o and L = 1, the register shifts left. If R = L = o or R = L = 1, the register holds its state.
2. Write a VHDL module for a 6-bit accumulator with carry-in (CI) and carry-out (CO). When Ad = o, the accumulator should hold its state. When Ad = 1, the accumulator should add the value of the data inputs D (plus CI) to the value already in the accumulator. The accumulator should also have an active-low asynchronous clear signal ClrN.