1. Write a VHDL module for a 4-bit up-down counter. If En = o, the counter will hold its state.If En = 1, the counter will count up if U = 1 or down if U = o. The counter should also have an asynchronous active-low clear signal ClrN.
2. Write a VHDL module for a 6-bit up-down counter. If U = 1and D = o, the counter will count up, and if U = o and D = 1, the counter will count down.If U = D = o or U = D = 1, the counter will hold its state.The counter should also have an asynchronous active-low preset signal PreN that sets all flip-flops to 1.