1 Write a VHDL model of a negative edge-triggered T-type flip-flop
2 Write a VHDL model of a 10-state synchronous counter that asserts an output when the count reaches 10.
3 Write a VHDL model of an N-bit counter with a control input ‘Up' . When the control input is '1' the counter. counts up; when it is '0' the counter counts down, The counter should not, however, wrap round. When the all 1s or all 0s states are reached the counter should stop.
Attachment:- Assignment.ppt