Need help with Verilog.
Part 1 - Odd Parity Generator a. Write a Verilog module for an odd parity generator circuit. The data message is 4 bits. Use Verilog bitwise operators. Do not use always blocks.
Part 2 - Even Parity Generator a. Write a Verilog module for an odd parity generator circuit. The data message is 4 bits. Use Verilog bitwise operators. Do not use always blocks.
Part 3 - Even Parity Checker a. Write a Verilog module for an even parity checker circuit. The received message is 5 bits. The four most significant bits are the data bits; the least significant bit is the parity bit.Use Verilog bitwise operators. Do not use always blocks.
Part 4 - Odd Parity Checker a. Write a Verilog module for an odd parity checker circuit. The received message is 5 bits. The four most significant bits are the data bits; the least significant bit is the parity bit. Use Verilog bitwise operators. Do not use always blocks.
Part 5 - Putting it all together c. Write a top level module to implement the circuit on an Altera FPGA board. You may need to instantiate additional circuits learned previously to complete this assignment.
a. Data messages:
There will be two different lines containing data messages. i. Data message 1: switches 3:0 ii. Data message 2: switches 7:4
b. Circuit operation and output:
i. Switch 8 selects which data message to transmit. ii. The transmitted data message contains the data bits and a parity bit. Switch 9 determines whether the parity is odd or even. iii. The parity error checker receives the transmitted message and displays its output value on HEX2. iv. The parity bit value is shown on HEX1. v. The data message is shown on HEX0. vi. An E is displayed on HEX3 for even parity and an O is displayed on HEX3 for odd parity. vii. Show the switch stated on the red LEDs
part 1
module part1_odd(A,B,C,D,CPE);
input A,B,C,D;
output CPE;
assign CPE = ~(A^B^C^D);
endmodule
part 2
module part2_even4bit(A,B,C,D,CPE);
input A,B,C,D;
output CPE;
assign CPE = (A^B^C^D);
endmodule
part 3
module part3_even5bit(A,B,C,D,EP,CPE);
input A,B,C,D,EP;
output CPE;
assign CPE = (A^B^C^D^EP);
endmodule
part 4
module part4_odd5bit(A,B,C,D,EP,CPE);
input A,B,C,D,EP;
output CPE;
assign CPE = ~(A^B^C^D^EP);
endmodule
7 seg
module hex_7seg_bitwise(A,B,C,D,i);
//input A, B, C, D;
input wire A,B,C,D;
// 7 bit signal
output [6:0]i;
//connect switches with bus
assign i[0] = (~A&~B&~C&D)|(~A&B&~C&~D)|(A&B&~C&D)|(A&~B&C&D);
assign i[1] = (B&C&~D)|(A&C&D)|(A&B&~D)|(~A&B&~C&D);
assign i[2] = (A&B&~D)|(A&B&C)|(~A&~B&C&~D);
assign i[3] = (~B&~C&D)|(B&C&D)|(A&~B&C&~D)|(~A&B&~C&~D);
assign i[4] = (~A&D)|(~B&~C&D)|(~A&B&~C);
assign i[5] = (~A&~B&D)|(~A&~B&C)|(~A&C&D)|(A&B&~C&D);
assign i[6] = (~A&~B&~C)|(~A&B&C&D)|(A&B&~C&~D);
endmodule
2 to 1 mux
module mux2to1(x,y,s,m);
input wire s;//select input
input wire x,y;// data input lines
output wire m;//output
//Internal signal decleration
assign m = (~s & x) | (s & y);
endmodule
This is what i have so far for part 5
part 5
module top_level(SW,LEDR,HEX0,HEX1,HEX2,HEX3);
input [9:0]SW;
output [9:0]LEDR ;
output [6:0]HEX0,HEX1,HEX2,HEX3;
assign LEDR = SW ;
wire [3:0]h;
wire [1:0]x;
wire [1:0]y;
wire E;
mux4to1_4bit inst8(SW[3:0],SW[8],h[3:0],HEX0);
mux4to1_4bit inst9(SW[4:7],SW[8],h[3:0],HEX0);
part1_odd inst0(h[3:0],x[0]);
part2_even4bit inst1(h[3:0],x[1]);
mux2to1 inst3(x[0],x[1],E,h[3:0],HEX1);
part3_even5bit inst4(E,y[0]);
part4_odd5bit inst5(E,y[1]);
mux2to1 inst6(y[0],y[1],HEX2);
hex_7seg_bitwise inst7 (1'b0,1'b0,1'b0,HEX0[6:0]);
hex_7seg_bitwise inst10 (SW[7:0],HEX0[6:0]);
endmodule