Write a Verilog behavioral dataflow model for a 4-bit expandable ALU. Create it using a hierarchical description that includes a behavioral dataflow model of an expandable 1-bit ALU.
The ALU must have the following functions:
000 F = A and B
001 F = A or B
010 F =~A
011 F = A xor B
100 F = A
101 F = B
110 F = A plus 1
111 F = A plus B