Problem
Write a data-?ow description (in both VHDL and Verilog) of a system that has three one-bit inputs, a(1), a(2), and a(3), and one one-bit output b. The least significant bit is a(1). The output b is 1 only when {a(l)a(2) a(3)} = 1, 2, 4, or 7 (all in decimal); otherwise, b is 0. Derive a minimized Boolean function of the system and write the data-?ow description. Simulate the system and verify that it works as designed. What is the function of this system?