1. Calculate the CPI for the processor in the table using: 1) only a first level cache,
2) a second level direct-mapped cache, and
3) a second level eight-way set associative cache. How do these numbers change if main memory access time is doubled? If it is cut in half?
2. It is possible to have an even greater cache hierarchy than two levels. Given the processor above with a second level, direct-mapped cache, a designer wants to add a third level cache that takes 50 cycles to access and will reduce the global miss rate to 1.3%. Would this provide better performance? In general, what are the advantages and disadvantages of adding a third level cache?