Draw a state diagram for an FSM with one input I that can stop the sequence when set to 0, and threeoutputs, X, Y, Z. XYZ should always follow the following sequence: 000, 001, 010, 100, repeat. When the input returns 1the sequence stops were it was left off. The output shouldchange only on a rising clock edge. Make 000 the initial state. Assume an implicit rising clock is ANDed with every FSM transition condition.