Problem
This question assumes that the logic blocks used to implement a processor's datapath have the following latencies:
I-Mem/D-Mem = 200ps,
Register File = 150ps,
Mux = 30ps, ALU = 200ps,
Adder = 150ps,
Single gate = 10ps,
Register Read = 30ps,
Register Setup = 20ps,
Sign Extend = 50ps, and
Control = 50ps.
What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)?