Q1. Suppose the addition of the two n-bit 2's complement numbers X=xn-1 xn-2 ... x1 x0 and Y=yn-1 yn-2 ... y1 y0. Suppose the sum is sn-1 sn-2 ... s1 s0 and the carry is cn cn-1 ... c2 c1.
(a) If X is positive, Y is negative, and cn-1 =0, what should be the values of cn and sn-1 ? Will overflow occur?
(b) If X is negative, Y is negative, and cn-1 =0, what should be the values of cn and sn-1 ? Will overflow occur?
(c) Subsequent the idea in part (a) and (b), please construct a truth table list the values of cn and sn-1 for all combinations of the sign of X, the sign of Y, and the value of cn-1. For each combination, please also state if overflow occurs or not.
(d) Based on the truth table in part (c), prove that Overflow = cn ? cn-1.
Q2. Design a circuit to add 1 to a given n-bit number (i.e., design an increment-by-1 circuit) using n half-adders.
Q3. Represent the decimal number -7.875 in IEEE 754 single-precision floating-point format.
Q4. What is the decimal value of the following IEEE 754 single-precision floating-point number? 00111111 01010000 00000000 00000000