What is Constrained-Random Verification ?
As ASIC and system-on-chip (SoC) designs continue to increase in size and complexity, there is an equal or greater increase in the size of verification effort required to achieve functional coverage goals. This has created a trend in RTL verification techniques to employ constrained-random verification, which shifts emphasis from hand-authored tests to utilization of compute resources.
With corresponding emergence of faster, more complex bus standards to handle the massive volume of data traffic there has also been a renewed significance for verification IP to speed time taken to develop advanced testbench environments which include randomization of bus traffic.