1. Consider the following design problem:
Using Active HDL 6.3 Student Edition or Xilinx Student Edition 6.31, write an ABEL, VHDL, or Verilog Program to design a clocked synchronous state machine with 2 inputs, X and Y and one output, Z. The output should be 1 if the number of 1 inputs on X and Y, since reset, is a multiple of 4. Otherwise the output should be 0.
Develop a lab report according to the following format:
LAB FORMAT
- The following format should be used for developing your lab report:
Title:
- A brief, concise, yet descriptive title
Statement of the Problem:
- What question(s) are you to answer?
Active HDL 3.0 Student Edition or Xilinx Student Edition 3.1 Functions Needed to Complete this Lab:
- What functions from either of the two digital design automation tools you used to complete this lab?
Hardware Description Language Program:
- A program you wrote in a hardware description language to solve the given design problem.
Schematic:
- The schematic generated through the use of the above mentioned hardware description language based program.
Conclusions: