A workstation uses a 15-MHZ processor with a claimed 10-MIPS rating to execute a given programme mix . Assume a one-cycle delay for each memory access.
1) what's effective CPI of this computer ?
2) processor is being upgraded with a 30-MHZ clock. However the speed of the memory subsystem remains unchanged, & consequently two clock cycles are needed per memory access. If 30% of the instruction required one memory access & another 5% required two memory access per instruction,what is the perfomance of the upgraded processor with a compatible instruction set &equal instruction counts .