Consider the circuit shown in Figure.
The input voltage vI is either 0.1 V or 2.5 V.
Assume gate voltages of φ = 2.5 V. The threshold voltages are VT N = -0.6 V for M4 and VT N = 0.4 V for all other transistors. The width-to-length ratios are 1 for M2 and M4, and 5 for MA and MB.
(a) What are the logic 1 values for vO1 and vO2?
(b) Design the width-to-length ratios of M1 and M3 such that the logic 0 values of vO1 and vO2 are 0.1 V.
![1885_Figure 2.jpg](https://secure.tutorsglobe.com/CMSImages/1885_Figure 2.jpg)