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What address in hex is required on the address bus in order


FIGURE shows how a 3 to 8 line decoder (74138) can be used in conjunction with NAND gate (74133) to connect a set of switches to the data bus of a microprocessor system via buffers (74367).

362_Three to Eight Line Decoder.jpg

Answer the following questions relating to the diagram:

a) What address, in HEX, is required on the address bus in order to read the switches?

b) (RD)‾ and (MEMRQ)‾ are control lines from the CPU. What must their logic state be in order to read the switches?

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This is an assignment about digital electronics. Here some circuit is given which is basically a memory interface circuit. this circuit accomplished with 3 to 8 line decoder (74138), NAND gate (74133) to connect a set of switches to the data bus of a microprocessor system via buffers (74367). Here the requirement is to define the HEX address to read the switches status.

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