Consider a four-input NMOS NAND logic gate with a depletion load similar to the circuit in Figure. The bias voltage is VDD = 3.3 V, and the threshold voltages are VTND = 0.4 V and VTNL = -0.6 V. The logic 0 output voltage is to be 0.10 V.
(a) Using approximation methods, determine K D/KL.
(b) The maximum power dissipation in the circuit is to be 100μW. Determine (W/L)L and (W/L)D.
