Problem: The purpose of this problem is to design a combinational logic circuit that converts a 4-bit binary code to an "inverted" gray code. In the context of this problem, an inverted gray code is the normal gray code in reverse (i.e. in the table above Binary = 111 would correspond with Gray = 000 instead of binary = 000). This can also be thought of as first taking the l's compliment of the binary code and then converting that to the gray code. For instance, a 2-bit inverted gray code is:
| Binary |
1's comp |
Inverted Gray Code |
| 000 |
111 |
100 |
| 001 |
110 |
101 |
| 010 |
101 |
111 |
| 011 |
100 |
110 |
| 100 |
011
|
010 |
| 101 |
010
|
011 |
| 110 |
001 |
001 |
| 111 |
000 |
000 |
Note that this is just the table presented above with outputs in reversed order from top to bottom.
a. Design a truth table for the circuit.
b. Use K-maps to determine an optimal equation for each output.
c. Convert each equation to use, at most, one gate.
d. Draw a circuit that implements each equation from part c.
e. Using the provided propagation delays, complete the timing diagram below for your circuit from part d. Each division on the diagram is 2 ns. Assume the initial values of the inputs have been unchanged for a very long time:
tpNoT = 0.5 ns tPAND = 1 ns tPoR = 0.5 ns tPxoR = 2.0 ns