Finite State Machines
Two data streams are coming serially to a system. These two streams are carefully observed and if considering any three bits from each stream, we observe that these two input streams are equal ; the FSM gives a signal to an alarm system to start warning the user. Overlapping conditions need to be considered.
A) Use Mealy state diagram and then construct the state table and state assigned table using one-hot encoding (you need to have only three states.
B) Draw the circuit by D-flip-flops through K-maps (you need, equal to the number of states,D-flip-flops in one hot-encoding)
Can you please explain what is going on because I have no idea?