The objective of this lab is for you to synthesize, download and test your FSMs designed iu Lab2. Except for the FSMs themselves, the code for Lab2_S is found on my webpage in file Lab2_S.zip. I have added the files m1605.vhd and m1605.ucf. The m1605.vhd file is the wrapper file that connects the seq_design file to the I0 on the FPGA. This file also makes reference to the LCD display controller and the CLK controller files. The seq_design file is slightly modified from the original one posted with Lab2. Additionally, you must modify FSM2 slightly from the Lab2 design. Instead of having the output go "high" and stay high after the UID is detected, the output will only go high for one CLK pulse. Then it must go low again. Additionally, the output should go high for one cycle when 16 logic "0"s are detected. Note that the phtses will trigger the display of your UID or ZERO on the LCD display. So, if your design is working correctly, the only things that should show up on the LCD display are the last four of your UID or "0000." The m1605.ucf file is the user constraint file that defines where the nil605.vhd I0 pins are assigned on the FPGA. Once your design is working, report the design statistics for the actual hardware implementation of the design.
To download your design onto the FPGA board, you will use the Impact Tool. The following steps will guide you through the process.
1. Synthesize the design (m1605.vhd) using the same steps you did for Lab l_S (in the ISE GUI make sure the "implementation" button is checked, make sure the m1605.vhd file is highlighted, and then double-click the create programming file in the lower left window.
2. After the bit file (m1605.bit) is generated, you will start Impact: Tools -> Impact (note: you can't start this tool until after the m1605.bit file is successfully created)
3. You may be asked if you want to take a survey? I suggest skipping the survey (No).
4. You will get a warning: No iMPACT project file exists -> OK
5. Open the Impact Wizard by selecting the button on the main iMPACT screen
6. Configure devices using Boundary-Scan (JTAG) -> OK
7. Auto Assign Configuration Files Query Dialog -> No
8. Device Programming Properties -> Cancel
9. To assign a congifiuration file to xc6v1x240t: Rt-click the xc6v1tx240t chip and then highlight: Assign New Configuration File
10. Double click: file_name.bit (note for this lab it should be called m1605.bit)
11. Attach SPI or BPI PROM -> No
12. To download the configuration file to xc6v1x240t: Rt-click xc6vIx240t chip and then select: program -> OK
13. After this step the FPGA should be programmed. Use the North Pushbutton to reset the circuit to initial states.
14. After you get your UID detector working. demonstrate it to the TA.
15. Turn in a report that details your estimated design requirements as compared to the actual number reported (this may take a little thinking because the stats provided by the tool include the support code provided in Lab.zip.
Attachment:- Lab.zip