The mixer phase detector characteristic shown in fig
Question: The mixer phase detector characteristic shown in Fig. exhibits a zero gain at the peaks, e.g., at ?φ = 0. A PLL using such a PD would therefore suffer from a zero loop gain at these points. Does this mean the PLL would not lock?
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question the mixer phase detector characteristic shown in fig exhibits a zero gain at the peaks eg at phi 0 a pll
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