Question: The following control signals arc associated with a CPU in a microcontroller. MEMRQ: asserted when a memory operation is ongoing IORQ: asserted when an If0 operation is ongoing WR: asserted when a write operation is ongoing RD: asserted when a read operation is ongoing ADROK: asserted output from an address decoder Write logic equations for the following:
a. A correctly timed latch signal for an output port.
b. A correctly timed three-state control signal for an input port.
c. A correctly timed signal to select memory for reading or writing.