The enhancement-load transistor in the NMOS inverter in given Figure has a separate bias applied to the gate. Assume transistor parameters of Kn = 1 mA/V2 for MD, Kn = 0.4 mA/V2 for ML, and VT N = 1 V for both transistors. Using the appropriate logic 0 and logic 1 input voltages, determine VO H and VO L for:
(a) VB = 4 V,
(b) VB = 5 V,
(c) VB = 6 V, and
(d) VB = 7 V.
