Consider Mb DRAM with a square layout (4096×4096). The word line parasitics are 60 Ohm/bit and 15fF/bit. The column line parasitics are 1 Ohm/bit and 12 fF/bit. Determine the minimum number of repeaters which must be inserted into the row lines such that the overall access line will be reduced to less than 0.2ns.
Consider a DRAM with 2^X bits. Rw = 65 Ohm/bit and Cw = 20fF/bit and Cb = 10fF/bit. Determine the optimum layout (rows, columns) such that tread (access time) is minimized. Apply your result to the case where X = 30 (how many rows and columns?).