The characteristic equations for a D flip-flop determine that the output Q is updated to either 0 or 1 after each clock cycle. A loadable D flip-flop has one additional input Load that allows data to be stored in the flip-flop for more than a single clock cycle. Design a loadable D flip-flop using anormal D flip-flop and some combinational logic. Use the charateristic equations for a D flop-flop as a starting point. When the input signal Load=1, the flip-flop functions as a normal D flip-flop. When the input signal Load=0, the output Q stays at it's previous value.