Question: The block diagram of a 512 × 8 RAM is shown in Figure. In this arrangement the memory unit is enabled only when CS1‾ = L and CS2 = H. Design a 1K × 8 RAM system using the 512 × 8 RAM as the building block. Draw a neat logic diagram of your implementation. Assume that the CPU can directly address 64K with an R/W‾ and eight data pins. Using linear decoding and don't-care conditions as 1's, determine the memory map in hexadecimal.
