Design a 3-bit 4:1 MUX using discrete logic gates (draw the circuit diagram). The 4 sources are I0 I1 I2 I3 and the output is Y (note that these are all 3-bit words). Individual bits of I0 are I0(0), I0(1), and I0(2); individual bits of I1 are I1(0), I1(1), and I1(2); and so on. The select signals are s1 s0 (s1 is the msb and s0 is the lsb). Thus, for example, if {s1 s0} = 10, then source I2 is routed to the output Y; if {s1 s0} = 01, then source I1 is routed to the output Y; and so on.