Suppose a 74LVC1G373 latch is used with VCC=3.3V. OE ispermanently tied to logic 0 and LE is permanently tied to logic 1.Also, the load capacitance is 15pF. Assume the D-input is connectedto a 30% duty cycle clock signal.
What is the maximum frequency of this clock signal if thelatch operates correctly as a transparent latch?
Here are some specs.
Tw = pulse duration, LE high min=3ns
Tsu = Setup time, data before LElow min=1.5ns
Th = Hold time, data after LElow min 1.5ns