Design a full address decoder for the following 68000 system.Show your address decoding table and the address range of eachdevice. Don't forget to show your gate-level design.
The system consists of :
256K Bytes of ROM using 128K X 8 chips
4M Bytes of RAM 1 using 512K X 4 Chips
4M Bytes of RAM2 using 1M X 1 chips
Hint: start by deciding how many chips are needed for eachgroup: ROM RAM1, and RAM2. Next, organize them into banks asneeded. Create a memory map and address table, assigning each groupor bank to a specific address range to avoid conflict. Finally design the logic necessary to produce the chip selects for each bank