Sketch hi-skew and lo-skew 3-input nand and nor gates what
1. Sketch HI-skew and LO-skew 3-input NAND and NOR gates. What are the logical efforts of each gate on its critical transition?
2. Derive a formula for gu, gd, and gavg for HI-skew and LO-skew k-input NAND gates with a skew factor of s
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