The D-type positive-edge-triggered flip-flop of Fig. 6-12 is modified by including an asynchronous-clear input in the circuit. The asynchronous-clear input is connected to a third input in gate 2 and also to a third input in gate 6.
(a) Draw the logic diagram of the flip-flop. including the asynchronous-cleat input.
(b) Analyze the circuit and show that when the asynchronous-clear input is logic-t). the Q output is cleared to 0 regardless of the values of the other two inputs. D and CP
(c) Show that when the asynchronous-clear input is logic-I. it has no effect on the normal operation of the circuit.
