Use the following code fragment:
Loop: LD R1,0(R2) ; load R1 from address 0+R2
DADDI R1,R1,#1 ; R1=R1+1
SD 0(R2),R1 ; store R1 at address 0+R2
DADDI R2,R2,#4 ; R2=R2+4
DSUB R4,R3,R2 ; R4=R3-R2
BNEZ R4,Loop ; branch to Loop if R4!=0
Assume that the initial value of R3 is R2+396.
(a) Show how a compiler would unroll the loop 4 times. Be sure to include the code that compute all of the pointers required for the operation within each iteration. Assume that the processor has as many registers as required.
(b) Show how a compiler would schedule the unrolled version of the loop from (a) for execution on a 4-wide VLIW processor that can execute an instruction on any execution unit. Assume latencies of 1 cycle for LD operation, and 0 cycle for DADDI and DSUB.