Problem #1
Given assembly language instructions :-
I1: lw $3, 100($5)
I2: add $6, $3, $2
I3: sub $9, $3, $8
I4: lw $1, 2000($9)
I5: add $5, $4, $3
I6: addi $7, $1, #8
a. Indicate all data dependencies (RAW, WAR, WAW) that exist between instructions.
b. Assume that the data is written in the first half-cycle and read in the second half-cycle. Show a pipeline execution diagram for the program by inserting nop instructions to eliminate the data hazard.
c. How many cycles does this code take to complete?
Problem #2
Given assembly language instructions :-
I1: lw $4, 8($16)
I2: lw $5, 16($4)
I3: add $2, $4, $5
a. indicate all data dependencies (RAW, WAR, WAW) that exist between instructions.
b. Insert nops to ensure correct execution of the code for a 5-stage pipeline system. Assume that the first half of the clock cycle write-back stage writes to register file and the second half of the clock cycle the decode stage performs a read of source registers.