5.1 Consider the timing diagram in Figure P5.1. Assuming that the D and Clock inputs shown are applied to the circuit in Figure 5.10, draw waveforms for the Qa , Qb, and Qc signals.
![536_59ea4847-28fe-42a8-98e8-b580d1fbf337.png](https://secure.tutorsglobe.com/CMSImages/536_59ea4847-28fe-42a8-98e8-b580d1fbf337.png)
Clock
D
Figure P5.1 Timing diagram for Problem 5.1.
5.2 Figure 5.4 shows a latch built with NOR gates. Draw a similar latch using NAND gates. Derive its characteristic table and show its timing diagram.
*5.3 Show a circuit that implements the gated SR latch using NAND gates only.