Leading-Ones Counter The circuit of figure 11.18must count the number of ‘ 1 ' s before a ‘ 0 'is found in a serial bit vector x. The vector is delimited by a data-valid bit (the counting must occur during all the time while dv = ‘ 1 ' ). Study the illustrative timing diagram included in the figure. Observe that dv and x (= " 111110000, "so N = 9) are updated at positive clock edges, which are the same edges at which the FSM must operate.
(a) Draw a state transition diagram for this machine.
(b) Based on your machine, complete the plots for y and pr_state in the figure.
(c) Say that we want the output value to remain stable (constant) during the computations, with the current value replaced only when a new value is ready. How can that be done? (Suggestion: see section 3.11.)
